## fx2_crossbar.py - the fx2 has four FIFOs, only one at a time can be written to or read to - i interpret this to mean you cannot read and write at the same time - fx2 crossbar coordinates up to 8 transfers at a time - delay between the fx2 and ice40 flags can't be avoided, so pipelining must be used - > The core of the difference is that ==the FPGA controls the FX2-side IN FIFO, but the host controls the OUT FIFO.== - > For IN FIFOs, the solution is to track the FIFO level on the FPGA using a counter - For OUT FIFOs, the solution is a skid buffer - a small additional FIFO that holds some additional writes Things that the fx2_crossbar gateware has to deal with: - Control signals that communicate the FX2's state to the ice40 - Switch between the addresses of the different FX2 FIFOs - Generate the strobe signals for the FX2: read, write, and packet end The FX2 crossbar state machine: ```mermaid flowchart LR SWITCH --> DRIVE DRIVE --> SETUP SETUP --> IN_XFER SETUP --> OUT_XFER IN_XFER --> SWITCH OUT_XFER --> SWITCH ``` http://www.cypress.com/file/138911/download#page=53 ![[CleanShot 2023-11-27 at [email protected]]] ## vendor datasheet part# from [[glasgow]]: cy7c68013A-56ltx [infineon link](https://www.infineon.com/cms/en/product/universal-serial-bus/usb-2.0-peripheral-controllers/ez-usb-fx2lp-fx2g2-usb-2.0-peripheral-controller/cy7c68013a-56ltxc/) [more technical info](https://www.infineon.com/dgdl/Infineon-EZ-USB_TECHNICAL_REFERENCE_MANUAL-AdditionalTechnicalInformation-v08_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0f9093657d61) ### architecture ![[CleanShot 2023-11-27 at [email protected]|grid]]![[CleanShot 2023-11-27 at [email protected]|grid]] - in their own datasheet, the vendor is calling this design ingenious. - as mentioned, there is a whole ass CPU in here. it's called an 8051 - the fx2 supports two USB modes: high speed (480 Mbps) and full speed (12Mbps). not low speed. - the clock is an external 24MHz crystal - a PLL gets you up to 480MHz ### ReNumeration TM - yes this name is patented. - this means that the FX2 - enumerates itself automatically when plugged in - downloads firmware over USB while in its default configuration - enumerates itself again, but as a different USB device based on the data it just downloaded - ta-da! ### endpoints ![[CleanShot 2023-11-27 at [email protected]]] ![[CleanShot 2023-11-27 at [email protected]]] takeaways: - EP0 = control endpoint - this endpoint has to accept all the standard requests defined in the USB spec Ch. 9 - EP1 = buffer or interrupt - Other endpoints have 512B buffers based on the Glasgow logs, two types of data transfers are happening: - bulk EP2 out - bulk EP6 in map of a USB transfer: ![[CleanShot 2023-11-27 at [email protected]]] ### FIFOs - FIFOs can be in master or slave mode (ew) - in M mode, FIFOADR is controlled internally by the GPIF - clock can be internal or external - ![[CleanShot 2023-11-27 at [email protected]]] - in S mode, the signals accepted are: - SLCS# - gates all of the other signals - SLRD - read, SLWR - write - can be synchronous logic or asynchronous strobes, depending on configuration - SLOE - output enable - must be inactive(low?) when writing data to a FIFO - PKTEND - packet end - ![[CleanShot 2023-11-27 at [email protected]]] ### GPIF > The GPIF is a flexible 8-bit or 16-bit parallel interface driven by a user-programmable finite state machine. thanks i hate it but not really outputs: - six control, CTL - nine addresses, GPIFADR - six ready, RDY > Each GPIF vector defines the state of the control outputs, and determines what state a ready input (or multiple inputs) must be before proceeding. a GPIF vector sounds kind of like an instruction. A sequence of GPIF "vectors" is called a "waveform" ## libfx2 https://libfx2.readthedocs.io/en/latest/introduction.html a few notes, although this is way over my head - firmware is read into the fx2 from a eeprom - i2c clock can be set to 100kHz or 400 kHz - fx2 has a whole ass cpu on it - the usb device VID and PID are set here