[[Glasgow Notes]] See also [[glasgow benchmark applet gate layout]] ## Benchmark Subtarget - Starts with defining signals for the register, FIFO, and Linear Feedback Shift Register - Goes on to a series of m.State and m.Case that specify what mode the system is in, either source, sink, or loopback - The first m.state sellects one of the m.case, and each m.case then sets n.next to it the intened state - The rest of the m.state are for Source, sinjk, and loopback individually. - Source - ![[CleanShot 2023-06-06 at [email protected]|lg]] - If the in fifo write ready is a 1, - In the combinatorial domain - Set the info write data equal to the Linear Feedback Shift Register word - Set the info write enable flag to 1 - Set the LFSR en to equal the register count [[bitwise and]] 1 - In the syncronous domain - Set the reg counter equal to itself +1 - Sink - ![[CleanShot 2023-06-06 at [email protected]|lg]] - If the out fifo is ready to be read - Check to see if the out fifo data does not equal the lsfr_word, and if it does not set the error signal to one - In the combinatorial domain - Set the out fifo read enable to 1 - Set the LFSR en to equal the register count [[bitwise and]] 1 - In the synchronous - Increment the register up one - Loopback - ![[CleanShot 2023-06-06 at [email protected]|lg]] - in the combinatorial domain - Take the data coming to glasgow from the out fifo, and set that equal to the in fifo - If the in fifo is write ready, and the out fifo is ready to be read, - in the combinorail domain - Set the in fifo write to enable - Set the out fifo read to enable - In the sync - Increment the reg count - Else - In the combinatorial domain - Set the in fifo flush to 1 - What actually reads the data from the source - ![[CleanShot 2023-06-06 at [email protected]]] - If mode is equal to source - await writing to the device to set the mode to source - await the interface resetting - Set counter_fut =