## [[2023-10-13]] - We want to add resistors in series with all of the data pins to limit the total fault current that can (and has) (and will) happen when we have both the ICE40 and the Data latch output drivers enabled at the same time. - The two fault conditions that could lead to damage are - Glasgow se7ts logic high while the ADC buffer is pulling the rails down - The ADC buffer sets logic high while glasgow sets logic low - So how much resistance do we need to current limit these conditions, and how many watts does that work out to so we can know what size of resistor we can get away with. In this case smaller is better. - See [[iCE40HX8k#Singled ended output DC characteristics]] for some more info:![[iCE40HX8k#Singled ended output DC characteristics]] - Also [[iCE40HX8k#LVDS recommended resistor values]] might be of use ![[iCE40HX8k#LVDS recommended resistor values]] ## [[2023-06-14]] - Started with the design for the LVDS adaptor board - Deleted all of the transceivers - Duplicated the output connector 3x - Using the through board version of connector to attach to the LVDS pins - looking at using [[Samtec SAM15552-ND]] - Adapted the existing glasgow footprint to the receptacal back entry design - [ ] need to move 3.3v on headers - [ ] Need to configure for 3.3 supply/source on headerse - ![[CleanShot 2023-06-15 at [email protected]]] - ![[CleanShot 2023-06-15 at [email protected]]] - ![[Pasted image 20230615020856.png]]